1. Field of the Invention
The present invention relates to a ferroelectric memory cell and more particularly, to a nonvolatile memory cell using a ferroelectric material as a dielectric placed between a pair of conductive electrodes, which enables to serve as a multi-bit cell, and reading and writing methods thereof.
2. Description of the Prior Art
A ferroelectric has in the ferroelectric state a property that the plot of an electric polarization (or stored charge) versus an electric field (or voltage) shows a hysteresis loop. Specifically, the induced polarization remains even when the electric field or voltage is reduced or increased from saturation to zero, and the direction (or polarity) of the remanent polarization depends upon the past history of the ferroelectric.
Conventionally, the distinctive property of the ferroelectric has been applied to semiconductor nonvolatile memory devices.
A conventional semiconductor nonvolatile memory device using the distinctive property of the ferroelectric has the following basic configuration. A plurality of memory cells, each of which has a single capacitor for storing an information, are arranged in a matrix array. The ferroelectric is used as the dielectric placed between a pair of conductive electrodes and therefore, this capacitor is termed a "ferroelectric capacitor". Also, the memory cell containing the ferroelectric capacitor is termed as a "ferroelectric memory cell".
To access the respective memory cells, necessary interconnection lines such as word lines, bit lines and other relating lines are arranged in the vicinity of the array of the memory cells.
FIG. 1 shows an equivalent circuit of the conventional memory cell of this sort. FIG. 2 shows the plot of stored charges Q versus an applied voltage V, i.e., the V-Q characteristic, of the conventional cell of FIG. 1.
As shown in FIGS. 1 and 2, the conventional memory cell is composed of a single ferroelectric capacitor, and its V-Q characteristic shows a hysteresis loop. In FIG. 2, the characters V.sub.c and -V.sub.c are the reverse voltages at which the stored charge Q is reduced to zero when the applied voltage V is reduced or increased from saturation, respectively. The characters Q.sub.r and -Q.sub.r are the stored or remanent charges when the applied voltage V is reduced or increased to zero from saturation, respectively.
It is seen from FIG. 2 that if two values of a binary data are assigned to the two remanent charges Q.sub.r and -Q.sub.r, respectively, the data can be stored in the ferroelectric capacitor. This is the basic concept of the semiconductor ferroelectric nonvolatile memory device.
With the ferroelectric nonvolatile memory device, each memory cell of which contains the ferroelectric capacitor, the cells are usually accessed in the following manner.
Specifically, on a write operation, a suitable pulse of a voltage is applied to a specified one of the cells, thereby inducing a positive or negative remanent polarization (or charge) in the corresponding cell. On a read operation, a suitable pulse of a voltage is applied to a specified one of the cells and an electric current flowing from the corresponding cell due to the stored charge is detected. The magnitude of this current changes dependent upon the presence or absence of the remanent polarization (or charge) and as a result, it can be known whether the cell has the remanent polarization (i.e., stored data value) or not through detection of the current.
To ensure the access to the respective memory cells, selection transistors may be additionally provided for the respective cells. Also, to improve the reliability for the access or read/write performance, dummy memory cells may be provided for the respective cells. Also in these cases, the basic configuration and the read/write operations described above are employed.
The conventional semiconductor ferroelectric nonvolatile memory device described here was, for example, disclosed in the Japanese Non-Examined Patent Publication No. 1-158691 published in June, 1989.
With the conventional ferroelectric memory device, each of the memory cells can store only one data value therein, in other words, each of the memory cells is a single-bit one. This fact causes the following problems when a large number of the memory cells are integrated on a large scale on a semiconductor substrate.
To large-scale integrate the memory cells on the substrate, it is important that the chip area per information (or bit) is as small as possible. With the above conventional memory device, the number of the cells needs to be increased in order to enhance the integration scale. Also, one set of relating interconnection lines is necessary for each of the single-bit cells. Therefore, the chip area per device becomes large with the increasing number of the integrated cells. This means that it is difficult to enhance the integration scale because of the chip area for the relating interconnection lines.
Additionally, because of the difficulty in integration scale enhancement, the fabrication cost per bit increases.